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integrated circuit systems, inc. ics950703 0690c?01/14/03 recommended application: intel tehema and tehema-e chipsets output features: 4 differential cpu clock pairs @ 3.3v 2 - 3v mref clocks for memory reference seeds, (separate single ended but 180 degrees out of phase) 4 - 66mhz 3v66 output 10 - 3v 33mhz pci clocks 2 - 48mhz clocks (180 degrees out of phase) 2 - 14.318 reference output (180 degrees out of phase) key specifications: ? 3v66 output jitter <300ps cpu output jitter <200ps mref output jitter <250ps programmable timing control hub tm for p4 tm features/benefits: quadrom tm frequency selection. programmable asynchronous 3v66/pci frequency. programmable output frequency. programmable output divider ratios. programmable output rise/fall time. programmable output skew. programmable spread percentage for emi control. programmable watch dog safe frequency. support i 2 c index read/write and block read/write operations. uses external 14.318mhz reference input. frequency table bit4 bit3 bit2 bit1 bit0 cpu mref agp pci sel133/100 fs3 fs2 fs1 fs0 mhz mhz mhz mhz 0 0 0 0 0 90.00 45.00 30.00 60.00 0 0 0 0 1 100.00 50.00 33.33 66.67 0 0 0 1 0 100.90 50.45 33.63 67.27 0 0 0 1 1 103.00 51.50 34.33 68.67 00100 105.00 52.50 35.00 70.00 0 0 1 0 1 108.00 54.00 36.00 72.00 0 0 1 1 0 110.00 55.00 36.67 73.33 0 0 1 1 1 112.00 56.00 37.33 74.67 0 1 0 0 0 115.00 57.50 38.33 76.67 0 1 0 0 1 118.00 59.00 39.33 78.67 0 1 0 1 0 120.00 60.00 40.00 80.00 0 1 0 1 1 122.00 61.00 40.67 81.33 0 1 1 0 0 125.00 62.50 41.67 83.33 0 1 1 0 1 127.00 63.50 42.33 84.67 0 1 1 1 0 130.00 65.00 43.33 86.67 0 1 1 1 1 133.60 66.80 44.53 89.07 10000 120.00 60.00 30.00 60.00 10001 133.33 66.67 33.33 66.67 1 0 0 1 0 133.90 66.95 33.48 66.95 10011 136.00 68.00 34.00 68.00 10100 138.00 69.00 34.50 69.00 10101 140.00 70.00 35.00 70.00 10110 142.00 71.00 35.50 71.00 10111 144.00 72.00 36.00 72.00 11000 145.00 72.50 36.25 72.50 1 1 0 0 1 148.00 74.00 37.00 74.00 1 1 0 1 0 150.00 75.00 37.50 75.00 1 1 0 1 1 152.00 76.00 38.00 76.00 1 1 1 0 0 154.00 77.00 38.50 77.00 1 1 1 0 1 156.00 78.00 39.00 78.00 1 1 1 1 0 158.00 79.00 39.50 79.00 11111 160.00 80.00 40.00 80.00 product preview documents contain information on new products in the sampling or preproduction phase of development. characteristic data and o ther specifications are subject to change without notice. gnd 1 56 vddmref multsel0/ref0 2 55 3vmref multsel1/ref1 3 54 3vmref_b vddref 4 53 gndmref x1 5 52 sclk x2 6 51 cpuclkt3 gndref 7 50 cpuclkc3 pciclk0 8 49 vddcpu pciclk1 9 48 cpuclkt2 vddpci 10 47 cpuclkc2 pciclk2 11 46 gndcpu pciclk3 12 45 cpuclkt1 gndpci 13 44 cpuclkc1 pciclk4 14 43 vddcpu pciclk5 15 42 cpuclkt0 vddpci 16 41 cpuclkc0 pciclk6 17 40 gndcpu **fs2/pciclk7 18 39 iref gndpci 19 38 avdd **fs3/pciclk8 20 37 gnd **sel100_133#/pciclk9 21 36 vdd3v66 vddpci 22 35 3v66_3 sdata 23 34 3v66_2 gnd48 24 33 gnd3v66 *fs0/48mhz_0 25 32 gnd3v66 **fs1/48mhz_1 26 31 3v66_1 avdd48 27 30 3v66_0 pd# 28 29 vdd3v66 * internal pull-up resistor ** internal pull-down resistor pin configuration 56-ssop ics950703
2 integrated circuit systems, inc. ics950703 0690c?01/14/03 power groups the ics950703 is a single chip clock solution for desktop designs using the intel brookdale chipset with rambus rdram memory. it provides all necessary clock signals for such a system. the ics950703 is part of a whole new line of ics clock generators and buffers called tch? (timing control hub). this part incorporates ics's newest clock technology which offers more robust features and functionality. employing the use of a serially programmable i 2 c interface, this device can adjust the output clocks by configuring the frequency setting, the output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each individual output cloc k. m/ n control can configure output frequency with resolution up to 0.1mhz increment. this part also provides 128 frequency selectio ns via ics quadrom tm technology as an alternate to m/n programming. general description block diagram pll2 frequency dividers programmable spread pll1 programmable frequency dividers stop logic x1 x2 xtal multsel (1:0) fs (3:0) sdata sclk pd# sel100_133# control logic 48mhz (1:0) ref (1:0) pciclk (9 :0) 3v66 (3:0) mref_b mref i ref 4 4 cpuclkt (3:0) cpuclkc (3:0) avdd gnd 4 7 ref output, crystal 27 24 48mhz fixed, fixed pll 38 37 cpu pll, cpu master clock, vdd gnd -- 10, 16, 22 13, 19 pci outputs 29, 36 32, 33 3v66 outputs 43, 49 40, 46 cpu outputs, iref, multsel 56 53 mref outputs pin number description
integrated circuit systems, inc. ics950703 0690c?01/14/03 pin description 3 pin pin pin # name type 1 gnd pwr ground pin. 2 multsel0/ref0 i/o 3.3v lvttl input for selection the current multiplier for cpu outputs / 14.318 mhz reference clock. 3 multsel1/ref1 i/o 3.3v lvttl input for selection the current multiplier for cpu outputs / 14.318 mhz reference clock. 4 vddref pwr ref, xtal power supply, nominal 3.3v 5 x1 i/o frequency select latch input pin / 3.3v pci free running clock output. 6 x2 i/o frequency select latch input pin / 3.3v pci free running clock output. 7 gndref pwr ground pin for the ref outputs. 8 pciclk0 out pci clock output. 9 pciclk1 i/o watchdog enable latch input/ 3.3v pci clock output. 10 vddpci pwr power supply for pci clocks, nominal 3.3v 11 pciclk2 out pci clock output. 12 pciclk3 out pci clock output. 13 gndpci pwr ground pin for the pci outputs 14 pciclk4 out pci clock output. 15 pciclk5 out pci clock output. 16 vddpci pwr power supply for pci clocks, nominal 3.3v 17 pciclk6 out pci clock output. 18 **fs2/pciclk7 i/o frequency select latch input pin / 3.3v pci clock output. 19 gndpci pwr ground pin for the pci outputs 20 **fs3/pciclk8 i/o frequency select latch input pin / 3.3v pci clock output. 21 **sel100_133#/pciclk9 i/o latched select input for 100 or 133.3mhz selection. 0=133mhz, 1 = 100mhz / 3.3v pci clock output. 22 vddpci pwr power supply for pci clocks, nominal 3.3v 23 sdata i/o data pin for i2c circuitry 5v tolerant 24 gnd48 pwr ground pin for the 48mhz outputs 25 *fs0/48mhz_0 i/o frequency select latch input pin / fixed 48mhz clock output. 3.3v 26 **fs1/48mhz_1 i/o frequency select latch input pin / fixed 48mhz clock output. 3.3v 27 avdd48 pwr power for 24/48mhz outputs and fixed pll core, nominal 3.3v 28 pd# in asynchronous active low input pin used to power down the device into a low power state. the internal clocks are disabled and the vco and the crystal are stopped. the latency of the power down will not be greater than 1.8ms. * internal pull-up resistor ** internal pull-down resistor ~ this output has 2x drive description
4 integrated circuit systems, inc. ics950703 0690c?01/14/03 pin description (continued) pin pin pin #nametype 29 vdd3v66 pwr power pin for the 3v66 clocks. 30 3v66_0 out 3.3v 66.66mhz clock output 31 3v66_1 out 3.3v 66.66mhz clock output 32 gnd3v66 pwr ground pin for the agp outputs 33 gnd3v66 pwr ground pin for the agp outputs 34 3v66_2 out 3.3v 66.66mhz clock output 35 3v66_3 out 3.3v 66.66mhz clock output 36 vdd3v66 pwr power pin for the 3v66 clocks. 37 gnd pwr ground pin. 38 avdd pwr 3.3v analog power pin for core pll 39 iref out this pin establishes the reference current for the cpuclk pairs. this pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 40 gndcpu pwr ground pin for the cpu outputs 41 cpuclkc0 out "complementary" clocks of differential pair cpu outputs. these are current mode outputs. external resistors are required for voltage bias. 42 cpuclkt0 out "true" clocks of differential pair cpu outputs. these are current mode outputs. external resistors are required for voltage bias. 43 vddcpu pwr supply for cpu clo cks, 3.3v nominal 44 cpuclkc1 out "complementary" clocks of differential pair cpu outputs. these are current mode outputs. external resistors are required for voltage bias. 45 cpuclkt1 out "true" clocks of differential pair cpu outputs. these are current mode outputs. external resistors are required for voltage bias. 46 gndcpu pwr ground pin for the cpu outputs 47 cpuclkc2 out "complementary" clocks of differential pair cpu outputs. these are current mode outputs. external resistors are required for voltage bias. 48 cpuclkt2 out "true" clocks of differential pair cpu outputs. these are current mode outputs. external resistors are required for voltage bias. 49 vddcpu pwr supply for cpu clo cks, 3.3v nominal 50 cpuclkc3 out "complementary" clocks of differential pair cpu outputs. these are current mode outputs. external resistors are required for voltage bias. 51 cpuclkt3 out "true" clocks of differential pair cpu outputs. these are current mode outputs. external resistors are required for voltage bias. 52 sclk in clock pin of i2c circuitry 5v tolerant 53 gndmref pwr ground pin for the 3vmref outputs. 54 3vmref_b out 3v reference output to memory clock driver (180 degree out of phase with 3vmref) 55 3vmref out 3v reference output to memory clock driver 56 vddmref pwr power supply for 3vmref clocks, nominal 3.3v * internal pull-up resistor ** internal pull-down resistor ~ this output has 2x drive description
5 integrated circuit systems, inc. ics950703 0690c?01/14/03 maximum allowed current n o i t i d n o c n o i t p m u s n o c y l p p u s v 3 . 3 x a m , s d a o l p a c e t e r c s i d x a m v 5 6 4 . 3 = d d v d n g r o d d v = s t u p n i c i t a t s l l a e d o m n w o d r e w o p ) 0 = # n w d r w p ( a m 0 4 e v i t c a l l u f a m 0 6 3 cpuclk swing select functions 0 l e s t l u m 1 e t y b 3 t i b t e g r a t d r a o b z m r e t / e c a r t , r e c n e r e f e r = f e r i ) r r * 3 ( / d d v t u p t u o t n e r r u c , z @ h o v a m 2 3 . 2 = f e r i 00 s m h o 0 6 % 1 5 7 4 = r r a m 2 3 . 2 = f e r i f e r i * 4 = h o i0 6 @ v 6 5 . 0 00 s m h o 0 5 % 1 5 7 4 = r r a m 2 3 . 2 = f e r i f e r i * 4 = h o i0 5 @ v 7 4 . 0 01 s m h o 0 6 % 1 5 7 4 = r r a m 2 3 . 2 = f e r i f e r i * 6 = h o i0 6 2 / v 5 8 . 0 01 s m h o 0 5 % 1 5 7 4 = r r a m 2 3 . 2 = f e r i f e r i * 6 = h o i0 5 @ v 1 7 . 0 10 s m h o 0 6 % 1 5 7 4 = r r a m 2 3 . 2 = f e r i f e r i * 5 = h o i0 6 @ v 1 7 . 0 10 s m h o 0 5 % 1 5 7 4 = r r a m 2 3 . 2 = f e r i f e r i * 5 = h o i0 5 @ v 9 5 . 0 11 s m h o 0 6 % 1 5 7 4 = r r a m 2 3 . 2 = f e r i f e r i * 7 = h o i0 6 @ v 9 9 . 0 11 s m h o 0 5 % 1 5 7 4 = r r a m 2 3 . 2 = f e r i f e r i * 7 = h o i0 5 @ v 2 8 . 0 00 ) v i u q e c d ( 0 3 % 1 1 2 2 = r r a m 5 = f e r i f e r i * 5 = h o i0 3 @ v 5 7 . 0 00 ) v i u q e c d ( 5 2 % 1 1 2 2 = r r a m 5 = f e r i f e r i * 5 = h o i0 2 @ v 2 6 . 0 01 ) v i u q e c d ( 0 3 % 1 1 2 2 = r r a m 5 = f e r i f e r i * 6 = h o i0 3 @ v 0 9 . 0 01 ) v i u q e c d ( 5 2 % 1 1 2 2 = r r a m 5 = f e r i f e r i * 6 = h o i0 2 @ v 5 7 . 0 10 ) v i u q e c d ( 0 3 % 1 1 2 2 = r r a m 5 = f e r i f e r i * 4 = h o i0 2 @ 0 6 . 0 10 ) v i u q e c d ( 5 2 % 1 1 2 2 = r r a m 5 = f e r i f e r i * 4 = h o i0 2 @ v 5 . 0 11 ) v i u q e c d ( 0 3 % 1 1 2 2 = r r a m 5 = f e r i f e r i * 7 = h o i0 3 @ v 5 0 . 1 11 ) v i u q e c d ( 5 2 % 1 1 2 2 = r r a m 5 = f e r i f e r i * 7 = h o i0 2 @ v 4 8 . 0 pin description
6 integrated circuit systems, inc. ics950703 0690c?01/14/03 general i 2 c serial interface information how to write: ? controller (host) sends a start bit. controller (host) sends the write address d2 (h) ics clock will acknowledge controller (host) sends the begining byte location = n ics clock will acknowledge controller (host) sends the data byte count = x ics clock will acknowledge controller (host) starts sending byte n through byte n + x -1 (see note 2) ics clock will acknowledge each byte one at a time controller (host) sends a stop bit how to read: controller (host) will send start bit. controller (host) sends the write address d2 (h) ics clock will acknowledge controller (host) sends the begining byte location = n ics clock will acknowledge controller (host) will send a separate start bit. controller (host) sends the read address d3 (h) ics clock will acknowledge ics clock will send the data byte count = x ics clock sends byte n + x -1 ics clock sends byte 0 through byte x (if x (h) was written to byte 8) . controller (host) will need to acknowledge each byte controllor (host) will send a not acknowledge bit controller (host) will send a stop bit *see notes on the following page . ics (slave/receiver) t wr ack ack ack ack ack p stop bit x byte index block write operation slave address d2 (h) beginning byte = n write start bit controller (host) byte n + x - 1 data byte count = x beginning byte n t start bit wr write rt repeat start rd read beginning byte n byte n + x - 1 n not acknowledge pstop bit slave address d3 (h) index block read operation slave address d2 (h) beginning byte = n ack ack data byte count = x ack ics (slave/receiver) controller (host) x byte ack ack
7 integrated circuit systems, inc. ics950703 0690c?01/14/03 notes: table1 continues on the next three pages. table1: quadrom frequency selection table bit6 bit5 bit4 bit3 bit2 bit1 bit0 cpu mref ag p pci x x sel133/100 fs3 fs2 fs1 fs0 mhz mhz mhz mhz 0 0 0 0 0 0 0 90.00 45.00 30.00 60.00 0 0 0 0 0 0 1 100.00 50.00 33.33 66.67 0 0 0 0 0 1 0 100.90 50.45 33.63 67.27 0 0 0 0 0 1 1 103.00 51.50 34.33 68.67 0 0 0 0 1 0 0 105.00 52.50 35.00 70.00 0 0 0 0 1 0 1 108.00 54.00 36.00 72.00 0 0 0 0 1 1 0 110.00 55.00 36.67 73.33 0 0 0 0 1 1 1 112.00 56.00 37.33 74.67 0 0 0 1 0 0 0 115.00 57.50 38.33 76.67 0 0 0 1 0 0 1 118.00 59.00 39.33 78.67 0 0 0 1 0 1 0 120.00 60.00 40.00 80.00 0 0 0 1 0 1 1 122.00 61.00 40.67 81.33 0 0 0 1 1 0 0 125.00 62.50 41.67 83.33 0 0 0 1 1 0 1 127.00 63.50 42.33 84.67 0 0 0 1 1 1 0 130.00 65.00 43.33 86.67 0 0 0 1 1 1 1 133.60 66.80 44.53 89.07 0 0 1 0 0 0 0 120.00 60.00 30.00 60.00 0 0 1 0 0 0 1 133.33 66.67 33.33 66.67 0 0 1 0 0 1 0 133.90 66.95 33.48 66.95 0 0 1 0 0 1 1 136.00 68.00 34.00 68.00 0 0 1 0 1 0 0 138.00 69.00 34.50 69.00 0 0 1 0 1 0 1 140.00 70.00 35.00 70.00 0 0 1 0 1 1 0 142.00 71.00 35.50 71.00 0 0 1 0 1 1 1 144.00 72.00 36.00 72.00 0 0 1 1 0 0 0 145.00 72.50 36.25 72.50 0 0 1 1 0 0 1 148.00 74.00 37.00 74.00 0 0 1 1 0 1 0 150.00 75.00 37.50 75.00 0 0 1 1 0 1 1 152.00 76.00 38.00 76.00 0 0 1 1 1 0 0 154.00 77.00 38.50 77.00 0 0 1 1 1 0 1 156.00 78.00 39.00 78.00 0 0 1 1 1 1 0 158.00 79.00 39.50 79.00 00 1 1111 160.00 80.00 40.00 80.00
8 integrated circuit systems, inc. ics950703 0690c?01/14/03 notes: continuation of table1 from previous page. quadrom tm frequency selection table n o i t p i r c s e d 6 t i b5 t i b4 t i b3 t i b2 t i b1 t i b0 t i b o c v z h m k l c u p c z h m 6 6 v 3 z h m k l c i c p z h m 0 0 1 / 3 3 1 l e s3 s f2 s f1 s f0 s f 0 1 0 0000 0 0 . 6 5 40 0 . 4 1 10 0 . 6 70 0 . 8 3 0 10 0001 0 0 . 0 6 40 0 . 5 1 17 6 . 6 73 3 . 8 3 0 10 0010 0 0 . 4 6 40 0 . 6 1 13 3 . 7 77 6 . 8 3 0 1 0 0011 0 0 . 8 6 40 0 . 7 1 10 0 . 8 70 0 . 9 3 0 10 0100 0 0 . 2 7 40 0 . 8 1 17 6 . 8 73 3 . 9 3 0 1 0 0101 0 0 . 6 7 40 0 . 9 1 13 3 . 9 77 6 . 9 3 0 10 0110 0 0 . 0 8 40 0 . 0 2 10 0 . 0 80 0 . 0 4 0 10 0111 0 0 . 4 8 40 0 . 1 2 17 6 . 0 83 3 . 0 4 0 10 1000 0 0 . 8 8 40 0 . 2 2 13 3 . 1 87 6 . 0 4 0 10 1001 0 0 . 2 9 40 0 . 3 2 10 0 . 2 80 0 . 1 4 0 1 0 10 10 0 0 . 0 0 50 0 . 5 2 13 3 . 3 87 6 . 1 4 0 10 1011 0 0 . 8 0 50 0 . 7 2 17 6 . 4 83 3 . 2 4 0 1 0 1100 0 0 . 6 1 50 0 . 9 2 10 0 . 6 80 0 . 3 4 0 10 1101 0 0 . 4 2 50 0 . 1 3 13 3 . 7 87 6 . 3 4 0 10 1110 0 0 . 2 3 50 0 . 3 3 17 6 . 8 83 3 . 4 4 0 1 0 1111 0 0 . 0 4 50 0 . 5 3 10 0 . 0 90 0 . 5 4 0 1 1 0000 0 0 . 6 5 40 0 . 2 5 10 0 . 6 70 0 . 8 3 0 110001 0 0 . 9 5 40 0 . 3 5 10 5 . 6 75 2 . 8 3 0 110010 0 0 . 2 6 40 0 . 4 5 10 0 . 7 70 5 . 8 3 0 1 1 0011 0 0 . 5 6 40 0 . 5 5 10 5 . 7 75 7 . 8 3 0 110100 0 0 . 8 6 40 0 . 6 5 10 0 . 8 70 0 . 9 3 0 1 1 0101 0 0 . 1 7 40 0 . 7 5 10 5 . 8 75 2 . 9 3 0 110110 0 0 . 4 7 40 0 . 8 5 10 0 . 9 70 5 . 9 3 0 110111 0 0 . 7 7 40 0 . 9 5 10 5 . 9 75 7 . 9 3 0 111000 0 0 . 0 8 40 0 . 0 6 10 0 . 0 80 0 . 0 4 0 111001 0 0 . 3 8 40 0 . 1 6 10 5 . 0 85 2 . 0 4 0 1 1 10 10 0 0 . 6 8 40 0 . 2 6 10 0 . 1 80 5 . 0 4 0 111011 0 0 . 9 8 40 0 . 3 6 10 5 . 1 85 7 . 0 4 0 1 1 1100 0 0 . 2 9 40 0 . 4 6 10 0 . 2 80 0 . 1 4 0 111101 0 0 . 5 9 40 0 . 5 6 10 5 . 2 85 2 . 1 4 0 111110 0 0 . 8 9 40 0 . 6 6 10 0 . 3 80 5 . 1 4 01 1 1111 0 0 . 1 0 50 0 . 7 6 10 5 . 3 85 7 . 1 4
9 integrated circuit systems, inc. ics950703 0690c?01/14/03 notes: continuation of table1 from previous page. quadrom tm frequency selection table n o i t p i r c s e d 6 t i b5 t i b4 t i b3 t i b2 t i b1 t i b0 t i b o c v z h m k l c u p c z h m 6 6 v 3 z h m k l c i c p z h m 0 0 1 / 3 3 1 l e s3 s f2 s f1 s f0 s f 1 0 0 0000 2 0 . 0 0 47 6 . 6 67 6 . 6 64 3 . 3 3 1 000001 0 0 . 8 0 40 0 . 8 60 0 . 8 60 0 . 4 3 1 000010 0 0 . 0 2 40 0 . 0 70 0 . 0 70 0 . 5 3 1 0 0 0011 0 0 . 2 3 40 0 . 2 70 0 . 2 70 0 . 6 3 1 000100 0 0 . 4 4 40 0 . 4 70 0 . 4 70 0 . 7 3 1 0 0 0101 0 0 . 6 5 40 0 . 6 70 0 . 6 70 0 . 8 3 1 000110 0 0 . 8 6 40 0 . 8 70 0 . 8 70 0 . 9 3 1 000111 0 0 . 0 8 40 0 . 0 80 0 . 0 80 0 . 0 4 1 00 1000 0 0 . 2 9 40 0 . 2 80 0 . 2 80 0 . 1 4 1 00 1001 0 0 . 4 0 50 0 . 4 80 0 . 4 80 0 . 2 4 1 0 0 10 10 0 0 . 6 1 50 0 . 6 80 0 . 6 80 0 . 3 4 1 00 1011 0 0 . 8 2 50 0 . 8 80 0 . 8 80 0 . 4 4 1 0 0 1100 0 0 . 0 4 50 0 . 0 90 0 . 0 90 0 . 5 4 1 00 1101 0 0 . 2 5 50 0 . 2 90 0 . 2 90 0 . 6 4 1 00 1110 0 0 . 4 6 50 0 . 4 90 0 . 4 90 0 . 7 4 1 0 0 1111 0 0 . 6 7 50 0 . 6 90 0 . 6 90 0 . 8 4 1 0 1 0000 0 0 . 8 8 50 0 . 8 90 0 . 8 90 0 . 9 4 1 010001 0 0 . 0 0 60 0 . 0 0 10 0 . 0 0 10 0 . 0 5 1 010010 0 0 . 2 1 60 0 . 2 0 10 0 . 2 0 10 0 . 1 5 1 0 1 0011 0 0 . 4 2 60 0 . 4 0 10 0 . 4 0 10 0 . 2 5 1 010100 0 0 . 6 3 60 0 . 6 0 10 0 . 6 0 10 0 . 3 5 1 0 1 0101 0 0 . 8 4 60 0 . 8 0 10 0 . 8 0 10 0 . 4 5 1 010110 0 0 . 0 6 60 0 . 0 1 10 0 . 0 1 10 0 . 5 5 1 010111 0 0 . 2 7 60 0 . 2 1 10 0 . 2 1 10 0 . 6 5 1 011000 8 6 . 6 6 67 6 . 6 6 17 6 . 6 63 3 . 3 3 1 011001 0 0 . 8 6 60 0 . 7 6 10 8 . 6 60 4 . 3 3 1 0 1 10 10 0 0 . 2 7 60 0 . 8 6 10 2 . 7 60 6 . 3 3 1 011011 0 0 . 6 7 60 0 . 9 6 10 6 . 7 60 8 . 3 3 1 0 1 1100 0 0 . 0 8 60 0 . 0 7 10 0 . 8 60 0 . 4 3 1 011101 0 0 . 4 8 60 0 . 1 7 10 4 . 8 60 2 . 4 3 1 011110 0 0 . 8 8 60 0 . 2 7 10 8 . 8 60 4 . 4 3 10 1 1 1 1 1 0 0 . 2 9 60 0 . 3 7 10 2 . 9 60 6 . 4 3
10 integrated circuit systems, inc. ics950703 0690c?01/14/03 notes: continuation of table1 from previous page. quadrom tm frequency selection table n o i t p i r c s e d 6 t i b5 t i b4 t i b3 t i b2 t i b1 t i b0 t i b o c v z h m k l c u p c z h m 6 6 v 3 z h m k l c i c p z h m 0 0 1 / 3 3 1 l e s3 s f2 s f1 s f0 s f 1 1 0 0000 0 0 . 6 9 60 0 . 4 7 10 6 . 9 60 8 . 4 3 1 10 0001 0 0 . 0 0 70 0 . 5 7 10 0 . 0 70 0 . 5 3 1 10 0010 0 0 . 4 0 70 0 . 6 7 10 4 . 0 70 2 . 5 3 1 1 0 0011 0 0 . 8 0 70 0 . 7 7 10 8 . 0 70 4 . 5 3 1 10 0100 0 0 . 2 1 70 0 . 8 7 10 2 . 1 70 6 . 5 3 1 1 0 0101 0 0 . 6 1 70 0 . 9 7 10 6 . 1 70 8 . 5 3 1 10 0110 0 0 . 0 2 70 0 . 0 8 10 0 . 2 70 0 . 6 3 1 10 0111 0 0 . 4 2 70 0 . 1 8 10 4 . 2 70 2 . 6 3 1 10 1000 0 0 . 0 2 30 0 . 0 6 13 3 . 3 57 6 . 6 2 1 10 1001 0 0 . 0 3 30 0 . 5 6 10 0 . 5 50 5 . 7 2 1 1 0 10 10 0 0 . 0 4 30 0 . 0 7 17 6 . 6 53 3 . 8 2 1 10 1011 0 0 . 0 5 30 0 . 5 7 13 3 . 8 57 1 . 9 2 1 1 0 1100 0 0 . 0 6 30 0 . 0 8 10 0 . 0 60 0 . 0 3 1 10 1101 0 0 . 0 7 30 0 . 5 8 17 6 . 1 63 8 . 0 3 1 10 1110 0 0 . 0 8 30 0 . 0 9 13 3 . 3 67 6 . 1 3 1 1 0 1111 0 0 . 0 9 30 0 . 5 9 10 0 . 5 60 5 . 2 3 1 1 1 0000 0 0 . 0 0 40 0 . 0 0 27 6 . 6 63 3 . 3 3 1 110001 0 0 . 2 0 40 0 . 1 0 20 0 . 7 60 5 . 3 3 1 110010 0 0 . 4 0 40 0 . 2 0 23 3 . 7 67 6 . 3 3 1 1 1 0011 0 0 . 6 0 40 0 . 3 0 27 6 . 7 63 8 . 3 3 1 110100 0 0 . 8 0 40 0 . 4 0 20 0 . 8 60 0 . 4 3 1 1 1 0101 0 0 . 2 1 40 0 . 6 0 27 6 . 8 63 3 . 4 3 1 110110 0 0 . 6 1 40 0 . 8 0 23 3 . 9 67 6 . 4 3 1 110111 0 0 . 0 2 40 0 . 0 1 20 0 . 0 70 0 . 5 3 1 111000 0 0 . 4 2 40 0 . 2 1 27 6 . 0 73 3 . 5 3 1 111001 0 0 . 8 2 40 0 . 4 1 23 3 . 1 77 6 . 5 3 1 1 1 10 10 0 0 . 2 3 40 0 . 6 1 20 0 . 2 70 0 . 6 3 1 111011 0 0 . 6 3 40 0 . 8 1 27 6 . 2 73 3 . 6 3 1 1 1 1100 0 0 . 0 4 40 0 . 0 2 23 3 . 3 77 6 . 6 3 1 111101 0 0 . 4 4 40 0 . 2 2 20 0 . 4 70 0 . 7 3 1 111110 0 0 . 8 4 40 0 . 4 2 27 6 . 4 73 3 . 7 3 11 1 1111 0 0 . 2 5 40 0 . 6 2 23 3 . 5 77 6 . 7 3
11 integrated circuit systems, inc. ics950703 0690c?01/14/03 i 2 c table: frequency select register pin # name control function t yp e0 1pwd bit 7 fs source frequency h/w iic select rw latch inputs iic 0 bit 6 fs6 freq select bit 6 rw 0 bit 5 fs5 freq select bit 5 rw 0 bit 4 fs4 freq select bit 4 rw 0 bit 3 fs3 freq select bit 3 rw 0 bit 2 fs2 freq select bit 2 rw 0 bit 1 fs1 freq select bit 1 rw 0 bit 0 fs0 freq selcet bit 0 rw 1 i 2 c table: spreading, device behavior and output control register pin # name control function t yp e0 1pwd bit 7 ss1 spread select 1 rw 0 bit 6 ss0 spread select 0 rw 0 bit 5 ssen spread enable control rw disable enable 0 bit 4 reserved reserved rw - - 0 bit 3 cput/c3 output control rw disable enable 1 bit 2 cput/c2 output control rw disable enable 1 bit 1 cput/c1 output control rw disable enable 1 bit 0 cput/c0 output control rw disable enable 1 - b y te 0 48/47 - - - - - see table 2: spread spectrum table - - - - - b y te 1 see table 1: quad rom tm frequency selection table - 51/50 45/44 42/41 i 2 c table: output control register pin # name control function t yp e0 1pwd bit 7 pciclk7 output control rw disable enable 1 bit 6 pciclk6 output control rw disable enable 1 bit 5 pciclk5 output control rw disable enable 1 bit 4 pciclk4 output control rw disable enable 1 bit 3 pciclk3 output control rw disable enable 1 bit 2 pciclk2 output control rw disable enable 1 bit 1 pciclk1 output control rw disable enable 1 bit 0 pciclk0 output control rw disable enable 1 12 18 17 15 b y te 2 14 11 9 8 table2: spread spectrum select ss1 ss0 (byte 1 bit 7) (byte 1 bit 6) 0 0 0.35% default 0 1 0.50% spread 2 1 0 0.70% spread 3 1 1 1.00% spread 4 spread % 0.32% downspread % 0.45% 0.75% 1.00% note
12 integrated circuit systems, inc. ics950703 0690c?01/14/03 i 2 c table: output control register pin # name control function t yp e0 1pwd bit 7 48mhz_1 output control rw disable enable 1 bit 6 48mhz_0 output control rw disable enable 1 bit 5 reserved reserved rw - - 0 bit 4 reserved reserved rw - - 1 bit 3 3vmref output control rw disable enable 1 bit 2 3vmref_b output control rw disable enable 1 bit 1 pciclk_9 output control rw disable enable 1 bit 0 pciclk_8 output control rw disable enable 1 i 2 c table: output control register pin # name control function t yp e0 1pwd bit 7 ref1 output control rw disable enable 1 bit 6 ref0 output control rw disable enable 1 bit 5 reserved reserved rw - - 1 bit 4 3v66_3 output control rw disable enable 1 bit 3 reserved reserved rw - - 1 bit 2 3v66_2 output control rw disable enable 1 bit 1 3v66_1 output control rw disable enable 1 bit 0 3v66_0 output control rw disable enable 1 i 2 c table: output control register pin # name control function t yp e0 1pwd bit 7 reserved reserved rw - - 0 bit 6 pll2en fix_2 pll control rw off on 1 bit 5 aen 3v66/pci freq source select rw cpu_pll sync fix_pll async 0 bit 4 afs4 async rom sel_2 rw 0 bit 3 afs3 async rom sel_1 rw 0 bit 2 afs2 async rom sel_0 rw 0 bit 1 afs1 async divider sel_1 rw 0 bit 0 afs0 async divider sel_0 rw 1 - 26 25 - b y te 3 55 54 21 20 3 2 - b y te 4 30 b y te 5 35 - 34 31 - - - - - - - - see table 3: async 3v66/pci frequency selection table
13 integrated circuit systems, inc. ics950703 0690c?01/14/03 table 3: async 3v66/pci frequency selection table byte 5 bit4 byte 5 bit3 byte 5 bit2 byte 5 bit1 byte 5 bit0 3v66 pci 0000 0 66.00 33.00 0000174.2537.13 0001 0 84.86 42.43 0001199.0049.50 0010064.0032.00 0010172.0036.00 0011082.2941.15 0011196.0048.00 0100059.2629.63 0100166.6733.34 0101076.1938.10 0101188.8944.45 0110067.2233.61 0110175.6337.82 0111086.4343.22 01111100.8350.42 1100070.0035.00 1100 1 78.75 39.38 1101 0 90.00 45.00 1 1 0 1 1 105.00 52.50 i 2 c table: read back register pin # name control function t yp e0 1pwd bit 7 wdhrb wd hard alarm status read back r- -x bit 6 multsel0 multsel0 read back r- -x bit 5 multsel1 multisel1 read back r- -x bit 4 sel100/ 133#rb sel100/133 # read back r- -x bit 3 fs3rb fs3 read back r - - x bit 2 fs2rb fs2 read back r - - x bit 1 fs1rb fs1 read back r - - x bit 0 fs0rb fs0 read back r - - x i 2 c table: vendor & revision id register pin # name control function t yp e0 1pwd bit 7 rid3 r - - 0 bit 6 rid2 r - - 0 bit 5 rid1 r - - 0 bit 4 rid0 r - - 1 bit 3 vid3 r - - 0 bit 2 vid2 r - - 0 bit 1 vid1 r - - 0 bit 0 vid0 r - - 1 - - - - - - - - - - - b y te 6 - - b y te 7 revision id vendor id - - -
14 integrated circuit systems, inc. ics950703 0690c?01/14/03 i 2 c table: byte count register pin # name control function t yp e0 1pwd bit 7 bc7 rw - - 0 bit 6 bc6 rw - - 0 bit 5 bc5 rw - - 0 bit 4 bc4 rw - - 0 bit 3 bc3 rw - - 1 bit 2 bc2 rw - - 1 bit 1 bc1 rw - - 1 bit 0 bc0 rw - - 1 i 2 c table: watchdog timer register pin # name control function t yp e0 1pwd bit 7 wd7 rw - - 0 bit 6 wd6 rw - - 0 bit 5 wd5 rw - - 0 bit 4 wd4 rw - - 0 bit 3 wd3 rw - - 1 bit 2 wd2 rw - - 0 bit 1 wd1 rw - - 1 bit 0 wd0 rw - - 0 i 2 c table: vco control select bit & wd timer control register pin # name control function t yp e0 1pwd bit 7 m/nen m/n programming enable rw disable enable 0 bit 6 wd enable wd enable rw disable enable 0 bit 5 wd sf mode wd safe frequency mode rw latched inputs b10 bit(4:0) 0 bit 4 wdsf4 rw - - 0 bit 3 wdsf3 rw - - 0 bit 2 wdsf2 rw - - 0 bit 1 wdsf1 rw - - 0 bit 0 wdsf0 rw - - 0 i 2 c table: vco frequency control register pin # name control function t yp e0 1pwd bit 7 ndiv8 n divider bit 8 rw - - x bit 6 mdiv6 rw - - x bit 5 mdiv5 rw - - x bit 4 mdiv4 rw - - x bit 3 mdiv3 rw - - x bit 2 mdiv2 rw - - x bit 1 mdiv1 rw - - x bit 0 mdiv0 rw - - x b y te 8 b y te 9 - - - - - - - - - - - - - b y te 10 writing to this register will configure how many bytes will be read back, default is 0f h = 15 bytes. - - - - these bits represent x*290ms the watchdog timer will wait before it goes to alarm mode. default is 10*290ms = 2.9 seconds. - - - - - - - - writing to these bit will configure the safe frequency as byte 0 bit (4:0) - b y te 11 the decimal representation of m div (6:0) + 2 is equal to reference divider value. default at power up = latch-in or byte 0 - - - - - -
15 integrated circuit systems, inc. ics950703 0690c?01/14/03 i 2 c table: vco frequency control register pin # name control function t yp e0 1pwd bit 7 ndiv7 rw - - x bit 6 ndiv6 rw - - x bit 5 ndiv5 rw - - x bit 4 ndiv4 rw - - x bit 3 ndiv3 rw - - x bit 2 ndiv2 rw - - x bit 1 ndiv1 rw - - x bit 0 ndiv0 rw - - x i 2 c table: spread spectrum control register pin # name control function t yp e0 1pwd bit 7 ssp7 rw - - x bit 6 ssp6 rw - - x bit 5 ssp5 rw - - x bit 4 ssp4 rw - - x bit 3 ssp3 rw - - x bit 2 ssp2 rw - - x bit 1 ssp1 rw - - x bit 0 ssp0 rw - - x i 2 c table: spread spectrum control register pin # name control function t yp e0 1pwd bit 7 reserved reserved r - - 0 bit 6 reserved reserved r - - 0 bit 5 ssp13 r - - x bit 4 ssp12 rw - - x bit 3 ssp11 rw - - x bit 2 ssp10 rw - - x bit 1 ssp9 rw - - x bit 0 ssp8 rw - - x i 2 c table: output divider control register pin # name control function t yp e0 1pwd bit 7 reserved reserved rw - - x bit 6 reserved reserved rw - - x bit 5 reserved reserved rw - - x bit 4 reserved reserved rw - - x bit 3 cpudiv3 rw x bit 2 cpudiv2 rw x bit 1 cpudiv1 rw x bit 0 cpudiv0 rw x these spread spectrum bits will program the spread pecentage. it is recommended to use ics spread % table for spread programming. cpu divider ratio can be configured via these 4 bits individually. see table 4: divider ratio combination table it is recommended to use ics spread % table for spread programming. - - - b y te 13 - - - - - - - - b y te 14 - - - - - - - - - - - b y te 15 - - - - b y te 12 the decimal representation of n div (8:0) +8 is equal to vco divider value. default at power up = latch-in or byte 0 rom table. - - - - - -
16 integrated circuit systems, inc. ics950703 0690c?01/14/03 table 4: divider ratio combination table (cpu & mref) bit 00 01 10 11 msb 1248 00 0000 2 0100 4 1000 8 1100 16 01 0001 3 0101 6 1001 12 1101 24 10 0010 5 0110 10 1010 20 1110 40 11 0011 7 0111 14 1011 28 1111 56 lsb address div address div address div address div divider (1:0) divider (3:2) i 2 c table: output divider control register pin # name control function t yp e0 1pwd bit 7 pcidiv3 rw x bit 6 pcibit 2 rw x bit 5 pcidiv4 rw x bit 4 pcibit 3 rw x bit 3 3v66div3 rw x bit 2 3v66div2 rw x bit 1 3v66div1 rw x bit 0 3v66div0 rw x i 2 c table: output divider control register pin # name control function t yp e0 1pwd bit 7 pciinv 3v66 pci 3v66 phase invert rw default inverse x bit 6 3v66inv 3v66 phase invert rw default inverse x bit 5 reserved reserved rw - - x bit 4 cpuinv cpu phase invert rw default inverse x bit 3 reserved reserved rw - - x bit 2 reserved reserved rw - - x bit 1 reserved reserved rw - - x bit 0 reserved reserved rw - - x i 2 c table: group skew control register pin # name control function t yp e0 1pwd bit 7 cpuskw1 rw 1 bit 6 cpuskw0 rw 1 bit 5 reserved reserved rw - - 1 bit 4 reserved reserved rw - - 1 bit 3 cpuskw1 rw 1 bit 2 cpuskw0 rw 1 bit 1 reserved reserved rw - - 1 bit 0 reserved reserved rw - - 1 cpuc/t(2:1) to cpu c/t(3,0) skew see table 5: 2-bit skew control table cpuc/t(3,0) to cpu c/t(2:1) skew see table 5: 2-bit skew control table pci divider ratio can be configured via these 4 bits individuall y . see table 4: divider ratio combination table 3v66 divider ratio can be configured via these 4 bits individuall y . see table 4: divider ratio combination table - - - b y te 16 - - - - - - b y te 17 - - - - - - - - - - b y te 18 - - - - -
17 integrated circuit systems, inc. ics950703 0690c?01/14/03 table 5: 2 bits skew programming table 4 step 0 1 lsb 0 0ps 250ps - 1 500ps 750ps - msb --- i 2 c table: group skew control register pin # name control function t yp e0 1pwd bit 7 mrefskw3 rw 0 bit 6 mrefskw2 rw 1 bit 5 mrefskw1 rw 0 bit 4 mrefskw0 rw 0 bit 3 reserved reserved rw - - 0 bit 2 reserved reserved rw - - 1 bit 1 reserved reserved rw - - 0 bit 0 reserved reserved rw - - 0 i 2 c table: group skew control register pin # name control function type 0 1 pwd bit 7 pciskw3 rw 0 bit 6 pciskw2 rw 1 bit 5 pciskw1 rw 1 bit 4 pciskw0 rw 0 bit 3 pciskw3 rw 0 bit 2 pciskw2 rw 1 bit 1 pciskw1 rw 1 bit 0 pciskw0 rw 0 cpuc/t to mref/mref_b skew cntrol see table 6: 7-steps skew control table - b y te 19 - - - - - - - - b y te 20 - - - - - - - see table 6: 7-steps skew control table see table 6: 7-steps skew control table cpu to pci(9:6) skew control cpu to pci(5:0) skew control table 6: 7-steps skew programming table 7 step 11 10 01 00 lsb 11 900 ps 750 ps 600 ps 450 ps 10 n/a n/a n/a 300 ps 01 n/a n/a n/a 150 ps 00 n/a n/a n/a 0.0 ps msb
18 integrated circuit systems, inc. ics950703 0690c?01/14/03 i 2 c table: group skew control register pin # name control function t yp e0 1pwd bit 7 3v66skw1 rw 0 bit 6 3v66skw0 rw 0 bit 5 reserved reserved rw - - 0 bit 4 reserved reserved rw - - 0 bit 3 3v66skw1 rw 0 bit 2 3v66skw0 rw 0 bit 1 reserved reserved rw - - 0 bit 0 reserved reserved rw - - 0 i 2 c table: slew rate control register pin # name control function t yp e0 1pwd bit 7 48mhzslw1 rw - - 1 bit 6 48mhzslw0 rw - - 0 bit 5 48mhzslw1 rw - - 1 bit 4 48mhzslw0 rw - - 0 bit 3 3v66slw1 rw - - 1 bit 2 3v66slw0 rw - - 0 bit 1 3v66slw1 rw - - 1 bit 0 3v66slw0 rw - - 0 i 2 c table: slew rate control register pin # name control function t yp e0 1pwd bit 7 reserved reserved rw - - 1 bit 6 reserved reserved rw - - 0 bit 5 pcislw1 rw - - 1 bit 4 pcislw0 rw - - 0 bit 3 pcislw1 rw - - 1 bit 2 pcislw0 rw - - 0 bit 1 pcislw1 rw - - 1 bit 0 pcislw0 rw - - 0 i 2 c table: slew rate control register pin # name control function t yp e0 1pwd bit 7 reserved reserved rw - - 0 bit 6 reserved reserved rw - - 0 bit 5 reserved reserved rw - - 0 bit 4 reserved reserved rw - - 0 bit 3 refslw1 rw - - 1 bit 2 refslw0 rw - - 0 bit 1 refslw1 rw - - 1 bit 0 refslw0 rw - - 0 pci (9:7), (5:2) slew rate control pci (6) slew rate control see table 5: 2-bit skew control table see table 5: 2-bit skew control table 48mhz_0 slew rate control 48mhz_1 slew rate control 3v66 (0) slew rate control 3v66 (3:1) slew rate control - b y te 21 - b y te 22 - - - - - - - - - - b y te 23 - - - - - - - - - - - - - b y te 24 ref0 slew rate control - - - - - - - ref1 slew rate control pci (1:0) slew rate control cpu to 3v66(3:2) skew control cpu to 3v66(1:0) skew control
19 integrated circuit systems, inc. ics950703 0690c?01/14/03 absolute maximum ratings supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd ?0.5 v to v dd +0.5 v ambient operating temperature . . . . . . . . . . . . 0c to +70c case temperature . . . . . . . . . . . . . . . . . . . . . . . . 115c storage temperature . . . . . . . . . . . . . . . . . . . . . ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operation al sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect p roduct reliability. electrical characteristics - input/supply/common output parameters t a = 0 - 70c; supply voltage v dd = 3.3 v +/-5% parameter symbol conditions min typ max units input high voltage v ih 2 v dd + 0.3 v input low voltage v il v ss - 0.3 0.8 v i ih v in = v dd ; inputs with no pull-down resistors -200 200 a i ih v in = v dd ; inputs with pull-down resistors 5ma i il1 v in = 0 v; inputs with no pull-up resistors -200 200 a i il2 v in = 0 v; inputs with pull-up resistors -5 ma i dd3.3op c l = full load; select @ 100 mhz 229 230 360 ma i dd3.3op c l =full load; select @ 133 mhz 220 233 360 ma powerdown current i dd3.3pd iref=5 ma 35 45 ma input frequency f i v dd = 3.3 v 14.318 mhz pin inductance l p in nh c in logic inputs 5 pf c out output pin capacitance 6 pf c inx x1 & x2 pins 27 36 45 pf clk stabilization 1,2 t stab from powerup or deassertion of powerdown to 1st clock. 13ms t pzh ,t pzl output enable delay (all outputs) 1 10 ns t phz ,t plz output disable delay (all outputs) 1 10 ns 1 guaranteed by design, not 100% tested in production. 2 see timin g dia g rams for buffered and un-buffered timin g re q uirements. delay 1 input capacitance 1 input low current input high current operating supply current
20 integrated circuit systems, inc. ics950703 0690c?01/14/03 electrical characteristics - cpu (0.7v select) t a = 0 - 70c; vdd=3.3v rs=33 ? , rp(pulldown) = 50 ? (unless otherwise stated) parameter symbol conditions min typ max units volta g e hi g hvhi g h 660 788 850 volta g e low vlow -150 16 150 max volta g e vovs 818 1150 min volta g evuds -450 11 rise time t r v ol = 0.175v, v oh = 0.525v 175 306 700 ps fall time t f v oh = 0.525v v ol = 0.175v 175 330 700 ps duty cycle d t3 measurement from differential wavefrom 45 50.2 55 % skew t sk3 v t = 50% 120 150 ps jitter, cycle to cycle t j c y c-c y c 1 v t = 50% 49 150 ps 1 guaranteed b y desi g n, not 100% tested in p roduction. 2 i owt can be varied and is selectable thru the multsel pin. mv statistical measurement on single ended signal using oscilloscope math function. measurement on single ended signal using absolute value. mv electrical characteristics - mref/mref_b t a = 0 - 70c; vdd=3.3v +/-5%; c l = 10-30 pf (unless otherwise specified) parameter symbol conditions min typ max units output frequency f o1 mhz output impedance r dsp1 1 v o = v dd *(0.5) 12 65 ? output high voltage v oh 1 i oh = -1 ma 2.4 v output low voltage v ol 1 i ol = 1 ma 0.4 v output high current i oh 1 v oh@min = 1.0 v, voh@max=3.135 -33 -33 ma output low voltage v oh@min = 1.95 v, voh@max=0.4 30 38 ma rise time t r1 1 v ol = 0.4 v, v oh = 2.4 v 0.5 1.8 2 ns fall time t f1 1 v oh = 2.4 v, v ol = 0.4 v 0.5 1.7 2 ns duty cycle d t1 1 v t = 1.5 v 45 54 55 % jitter t j c y c-c y c 1 v t = 1.5 v 3v66 138 250 ps 1 guaranteed b y desi g n, not 100% tested in p roduction.
21 integrated circuit systems, inc. ics950703 0690c?01/14/03 electrical characteristics - 3v66 t a = 0 - 70c; vdd=3.3v +/-5%; c l = 10-30 pf (unless otherwise specified) parameter symbol conditions min typ max units output frequency f o1 66.66 mhz output impedance r dsp1 1 v o = v dd *(0.5) 12 65 ? output high voltage v oh 1 i oh = -1 ma 2.4 v output low voltage v ol 1 i ol = 1 ma 0.4 v output high current i oh 1 v oh@min = 1.0 v, voh@max=3.135 -33 -33 ma output low voltage v oh@min = 1.95 v, voh@max=0.4 30 38 ma rise time t r1 1 v ol = 0.4 v, v oh = 2.4 v 0.5 1.8 2 ns fall time t f1 1 v oh = 2.4 v, v ol = 0.4 v 0.5 1.51 2 ns duty cycle d t1 1 v t = 1.5 v 45 50 55 % skew t sk1 1 v t = 1.5 v 52 250 ps jitter t j c y c-c y c 1 v t = 1.5 v 3v66 160 250 ps 1 guaranteed b y desi g n, not 100% tested in p roduction. electrical characteristics - 48mhz t a = 0 - 70c; vdd=3.3v +/-5%; c l = 10-20 pf (unless otherwise specified) parameter symbol conditions min typ max units output frequency f o1 14.32 mhz output impedance r dsp1 1 v o = v dd *(0.5) 20 60 ? output high voltage v oh 1 i oh = -1 ma 2.4 v output low voltage v ol 1 i ol = 1 ma 0.4 v output high current i oh 1 v oh@min = 1.0 v -29 -23 output low current i ol 1 v ol @min = 1.95 v 29 27 rise time t r1 1 v ol = 0.4 v, v oh = 2.4 v 11.154 ns fall time t f1 1 v oh = 2.4 v, v ol = 0.4 v 11.44 ns duty cycle d t1 1 v t = 1.5 v 45 52.5 55 % jitter t j c y c-c y c 1 v t = 1.5 v 184 350 ps 1 guaranteed b y desi g n, not 100% tested in p roduction.
22 integrated circuit systems, inc. ics950703 0690c?01/14/03 electrical characteristics - ref t a = 0 - 70c; vdd=3.3v +/-5%; c l = 10-20 pf (unless otherwise specified) parameter symbol conditions min typ max units output frequency f o1 14.32 mhz output impedance r dsp1 1 v o = v dd *(0.5) 20 60 ? output high voltage v oh 1 i oh = -1 ma 2.4 v output low voltage v ol 1 i ol = 1 ma 0.4 v output high current i oh 1 v oh@min = 1.0 v -29 -23 output low current i ol 1 v ol @min = 1.95 v 29 27 rise time t r1 1 v ol = 0.4 v, v oh = 2.4 v 11.14 ns fall time t f1 1 v oh = 2.4 v, v ol = 0.4 v 10.924 ns duty cycle d t1 1 v t = 1.5 v 45 46.4 55 % jitter t j c y c-c y c 1 v t = 1.5 v 192 1000 ps 1 guaranteed b y desi g n, not 100% tested in p roduction.
23 integrated circuit systems, inc. ics950703 0690c?01/14/03 fig. 1 shared pin operation - input/output pins the i/o pins designated by (input/output) serve as dual signal functions to the device. during initial power-up, they act as input pins. the logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. at the end of power-on reset, (see ac characteristics for timing values), the device changes the mode of operations for these pins to an output function. in this mode the pins produce the specified buffered clocks to external loads. to program (load) the internal configuration register for these pins, a resistor is connected to either the vdd (logic 1) power supply or the gnd (logic 0) voltage potential. a 10 kilohm (10k) resistor is used to provide both the solid cmos programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. via to vdd clock trace to load series term. res. programming header via to gnd device pad 2k 8.2k figure 1 shows a means of implementing this function when a switch or 2 pin header is used. with no jumper is installed the pin will be pulled high. with the jumper in place the pin will be pulled low. if programmability is not necessary, than only a single resistor is necessary. the programming resistors should be located close to the series termination resistor to minimize the current loop area. it is more important to locate the series termination resistor close to the driver than the programming resistor.
integrated circuit systems, inc. 24 ics950703 0690c?01/14/03 300 mil ssop package min max min max a2.412.80.095.110 a1 0.20 0.40 .008 .016 b 0.20 0.34 .008 .0135 c0.130.25.005.010 d e 10.03 10.68 .395 .420 e1 7.40 7.60 .291 .299 e h0.380.64.015.025 l0.501.02.020.040 n 0 8 0 8 min max min max 56 18.31 18.55 .720 .730 10 - 0 0 3 4 r ef erence d o c.: jedec pub licat io n 9 5, m o-118 variations see variations see variations n d mm. d (inch) see variations see variations 0.635 basic 0.025 basic symbol in millimeters in inches common dimensions common dimensions ordering information ics950703 y ft designation for tape and reel packaging package type f = ssop revision designator (will not correlate with datasheet revision) device type prefix ics = standard device example: ics xxxxxx y f - t index area index area 12 1 2 n d h x 45 h x 45 e1 e seating plane seating plane a1 a e -c- - c - b .10 (.004) c .10 (.004) c c l

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